1. Field of the Invention
The present invention relates to a process for producing an epitaxial wafer and more particularly to a method of controlling a misfit dislocation to be created in or near the interface between a semiconductor substrate of the epitaxial wafer and an epitaxial layer thereof during producing the epitaxial wafer.
2. Description of the Related Art
Recently, the so-called epitaxial wafer comprising a semiconductor substrate of a lower resistivity and an epitaxial layer of a higher resistivity has drawn an attention as a starting wafer for a high integrated DRAM or a high-speed CMOS device.
On the other hand, a metal impurity intrinsically contained in crystal or invading a wafer during producing the above semiconductor device is present at a junction in the wafer. The metal impurity causes various crystal defects and causes a current leakage or dielectric strength deterioration, so that the performance of the semiconductor device deteriorates. In order to avoid the deteriorations in the performnce of the semiconductor device various attempts have been taken for the wafer.
In particular, exemplifying an epitaxial wafer, it has been thought that since the epitaxial wafer has a structure in which an epitaxial growth layer is epitaxially interfaced with a semiconductor substrate, the top surface layer of the epitaxial layer in and on which a semiconductor device is fabricated is remote from the back surface of the semiconductor substrate. Therefore, creating an extrinsic deformation or strain on the back surface of the semiconductor substrate cannot produce a desired gettering effect. For example, A. S. Salih et al have stated this fact in PP. 419-421, Appl., Phys., Lett., Vol. 46, No. 4, Feb. 15, 1985.
On the other hand, H. Kikuchi et al have reported in PP. 463-465, Appl., Phys., Lett., Vol. 54, No.5,, Jan. 30, 1989 that they discovered in and near the interface between a high-doped and reduced crystal lattice spacing of the substrate of an p/p.sup.+ -structured epitaxial wafer and a normal crystal lattice spacing of the epitaxial growth layer of the p/p.sup.+ -structured epitaxial wafer and in particular, near the top surface of the substrate adjoining the epitaxial growth layer, a misfit dislocation caused by a misfit between the crystal lattice of the substrate and the normal crystal lattice of the epitaxial growth layer and that the misfit dislocation getters a metal impurity.
FIG.5 illustrates a schematic longitudinal section of a p/p.sup.+ -structured epitaxial wafer. In FIG.5, the epitaxial wafer generally indicated at 1 comprises a p.sup.+ -type semiconductor substrate 1a and a p-type epitaxial layer 1b deposited on one major surface of the semiconductor substrate 1a.
An impurity concentration of the semiconductor substrate 1a is 1.times.10.sup.18 atoms/cc or more and the other hand, an impurity (i.e., boron) concentration of the epitaxial layer 1b is about 1.times.10.sup.15 atoms/cc. The concentration difference is in or over three digits in the exponent of 10.
The p/p.sup.+ -structured epitaxial wafer 1 with such great impurity concentration difference is ready to create a misfit dislocation in the interface between the semiconductor substrate 1a and epitaxial layer 1b, which will depend on other specifications of the epitaxial wafer 1. This misfit dislocation getters a heavy metal present in the epitaxial wafer 1.
FIG.6 represents results of measurements of distributions of the concentration of intentionally doped Cu in the depth of the p/p.sup.+ -structured epitaxial layer and semiconductor substrate and the density of created misfit dislocation.
As apparent from FIG.6, the misfit dislocations are created in the interface between the semiconductor substrate 1a and epitaxial layer 1b, the distribution of the density of the misfit dislocation well matches that of the concentration of the Cu so that part of the interface having the peak distribution of the density of the misfit dislocation effectively getters the Cu.
The present inventors tested in detail how an epitaxial growth condition affects a creation of misfit dislocations and found out that the creation of misfit dislocations remarkably depended on a difference between impurity concentrations of an epitaxial growth layer and a substrate, the thicknesses of the epitaxial growth layer and substrate, etc.
The present inventors also found out that intrinsic misfit dislocations present in the epitaxial wafer were ununiform over the epitaxial wafer and the amount of the intrinsic misfit dislocations was small.
FIGS. 7 and 8 represent how the resistivity of a silicon crystal substrate and the thickness of an epitaxial layer characterizes the frequency of creation of misfit dislocations when a p-type and 10 .OMEGA.cm epitaxial layer is grown on each of 530 .mu.m p.sup.+ -type silicon crystal substrates with &lt;111&gt; and &lt;100&gt; crystal orientations. In FIGS. 7 and 8, the symbol of a white square represents the frequency of creation of 100 or more misfit dislocations in the case of the substrate of &lt;100&gt; crystal orientation, the symbol of a black square represents the frequency of creation of 100 or more misfit dislocations in the case of the substrate of &lt;111&gt; crystal orientation, the symbol of a white regular triangle represents the frequency of creation of above 50 and below 100 misfit dislocations in the case of the substrate of &lt;100&gt; crystal orientation, the symbol of a black regular triangle represents the frequency of creation of above 50 and below 100 misfit dislocations in the case of the substrate of &lt;111&gt; crystal orientation, the symbol of a white circle represents the frequency of creation of 50 or less misfit dislocations in the case of the substrate of &lt;100&gt; crystal orientation, and the symbol of a black circle represents the frequency of creation of 50 or less misfit dislocations in the case of the substrate of &lt;111&gt; crystal orientation. The values superimposed on the respective curves in broken lines represent bows of epitaxial wafers.
As apparent from FIGS. 7 and 8, the larger an epitaxial wafer bow, the greater the number of misfit dislocations. Herein, Lang's method of x-ray diffraction topography performs a (400) diffraction of the epitaxial wafer and took a topography throughout each of the epitaxial wafers so that the topographical images of misfit dislocations present in the epitaxial wafer were counted to provide the density of misfit dislocation of the epitaxial wafer.
As apparent from the above description, specifications of an epitaxial wafer decides the frequency of creation of intrinsic misfit dislocations in the epitaxial wafer. However, the gettering effect of only the intrinsic misfit dislocations present in the epitaxial wafer are insufficient as a due intrinsic gettering effect of the epitaxial wafer in producing an actual high integrated semiconductor circuit device. In addition, it is impractical that the specifications of the epitaxial wafer is selected to achieve the effective frequency of occurrence of intrinsic misfit dislocations, i.e., the intrinsic gettering operation of the epitaxial wafer.
Another gettering method for epitaxial wafer is the so-called IG method using a microdefect created by a precipitation of an oxygen concentration exceeding the solubility of oxygen in the epitaxial wafer. However, the IG method is impractical because of the ununiformity and the poor repeatability of a gettering effect throughout an epitaxial wafer.
In addition, a formation of a Ge mixed crystal layer during an epitaxial layer growth period, taught in the above report of A. S. Salih et al, uses the above-described misfit dislocation. This teaching entails a technological problem in determining the mixing ratio of the Ge mixed crystal and controlling the creation of a misfit dislocation thereby.
Therefore, an object of the present invention is to provide a method of effectively increasing and controlling the frequency of creation of misfit dislocation in and near the interface between the semiconductor substrate and an epitaxial layer with an impurity concentration different from that of the semiconductor substrate, in a process for producing an epitaxial wafer in which the epitaxial layer is deposited on the semiconductor substrate. The process of the present invention provides an actual means for gettering the epitaxial layer.